* Programmable CAS Latencies (3, 4 and 5), Burst Length (4 & 8) and Burst Type
* Auto Refresh (CBR) and Self Refresh
* Average Refresh Period 7.8 µs at a T lo.

devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E².

HYS72T32000HR

HYS72T32000HU

HYS72T32000GR

HYS72T32000GR-3-A

HYS72T32000GR-37-A

HYS72T32000GR-5-A

HYS72T128000GR

HYS72T128000GR-37-A

HYS72T128000GR-5-A

HYS72T128000HP2.5-B

HYS72T128000HP25F-B

HYS72T128000HP3-B

HYS72T128000HP3.7-B